Desirable design goals in electronic semiconductor manufacturing include a potential for significant cost reduction during the life of the design, high speed operation, low power consumption, and good reliability. In order to attain the goal of high speed operation, the many intermediate operations performed within the semiconductor device must be performed as quickly as possible, and with as little delay between operations as is practical to ensure reliable operation. Such intermediate operations may be synchronized by an internal clock signal. For example, if an output signal of a first intermediate operation is used as an input signal for a second intermediate operation, an internal clock signal may be utilized to synchronize the transfer of the output signal of the first intermediate operation to the input circuit of the second intermediate operation.
Unfortunately, increasing the speed of a semiconductor device is not as simple as increasing the speed of the internal clock which synchronizes the intermediate operations. One obstacle to increasing the speed of a semiconductor device is the amount of time required to transfer an output signal from a circuit performing a first intermediate operation to an input of a circuit performing a second intermediate operation.
One contributor to such a signal transfer delay is the operating speed of individual transistors within the semiconductor device. In many semiconductor devices, transistors are utilized in digital circuits in a manner that resembles an ordinary switch. However, such "transistor switches" do not "turn on" or "turn off" instantaneously; it takes a finite amount of time to move an electrical charge, which is sufficient to "turn on" or "turn off" the transistor, into or out of the semiconductor structure that forms the transistor. This time required to move a sufficient electrical charge to either "turn on" or "turn off" a transistor may be referred to as the transistor switching time and is typically in the range of a few nanoseconds.
In addition to high speed transistor operation, another semiconductor device design goal is to make the transistors within the device as small as practicable. A smaller transistor design allows designers to make devices having more transistors, and consequently, to make devices having greater functionality. There are problems, however, with fabricating devices with smaller transistors. For example, smaller transistors are more susceptible than larger transistors to manufacturing process variations, such as pattern alignment and chemical etching, during the many steps of semiconductor manufacturing. The reason for this increased susceptibility is that using a fabrication process step that produces transistor geometries accurate to within two units to fabricate a transistor that is, for example, one hundred units wide affects the electrical characteristics of that transistor proportionately less than using the same process step to fabricate a transistor that is ten units wide. Proportionately, the larger transistor's geometry is affected by two percent, while the smaller transistor's geometry is affected by twenty percent. Such process variations may cause the electrical properties of the transistors to vary, which may result in slower switching speeds.
Therefore, the overall speed of the device may be increased, but the uncertainty of transistor operating speed due to process variations may require designers to include an additional delay between intermediate operations to increase production yields. Production yield decreases as devices fail to function because of data errors, which may result from a signal transfer time increase in combination with a clock signal that prematurely clocks erroneous data into an input circuit. The timing involved in "clocking" signals between circuits is discussed in greater detail below.
In addition to the delay resulting from transistor switching time, semiconductor device speed may also be reduced by the electrical properties, such as capacitance and resistance, of interconnect lines within the semiconductor device. Interconnect lines may be conductors extending from a circuit in one part of the semiconductor device to a circuit in another part of the device, such as, for example, a "bit line" used to transfer data from a memory cell to a sense amplifier in a semiconductor memory device. A typical bit line extends from a memory cell, located in a memory array, across the memory array (which may be a substantial distance in terms of semiconductor geometries), to a sense amplifier, wherein such a transferred signal is prepared for transmission out of the semiconductor device. If an interconnect line has a relatively large intrinsic capacitance and resistance, it may take a considerable amount of time to transfer a signal via such an interconnect line. As the length of the interconnect line increases, the resistance and capacitance of the line may increase proportionately.
It is well known in the art of semiconductor design to utilize a clock signal to more precisely control the timing of intermediate operations, and the flow of input and output signals between circuits performing intermediate operations. Some clock signals within the semiconductor may be used to enable a circuit to "output" a signal, while other clock signals may be used to enable a circuit to receive or input a signal. Since it takes some time for a transistor to "turn on" an output signal after receiving an enabling output clock, and it takes some time for an output transistor to change the voltage of an interconnect line, an output signal from one circuit will not be immediately available as the input for a second circuit. Therefore, the clock signal utilized to enable the output a signal from a first circuit may not always be utilized as an input clock to enable the input of that same "output signal" into a second circuit. Stated differently, the clock signal for the input to the second circuit must occur sometime after the clock signal for the output of the first circuit so that the signal is allowed enough time to transfer between the two circuits.
To determine such a time difference between an output clock signal and an input clock signal, the designer must be able to calculate or predict transistor switching times, and the time necessary to "drive" or transfer the signal via the interconnecting line. Typically, once the designer has calculated the time required for a typical signal transfer, the designer includes an additional amount of time to compensate for variations in transistor switching times and "interconnect line drive times" which may occur due to variations in the numerous process steps required to make the semiconductor device.
In present semiconductor devices, the input clock signal may be delayed until such time as the output signal from the output circuit is likely to be present at the input circuit, considering worst-case process variations, which would cause a worst-case signal transfer time. Such worst-case process analysis includes the consideration of variations in process steps, such as chemical baths and mask alignment, which approach the extremes of process specifications, and the effect that such process variations may have on transistor switching times and the capacitance and resistance of interconnect lines.
As the semiconductor device is fabricated, it is subjected to a number of doping, layering, and patterning processes, each of which must meet stringent physical and cleanliness requirements. Such sophisticated processes will vary from one batch of semiconductor devices to another, resulting in speed variations from device to device. Even though the process is monitored and continually calibrated, some variation in the equipment and chemicals is inevitable. All of the tests and process specifications allow for some variation; that is, each semiconductor wafer experiences process variations, which may cause operational speed variations.
In the case of a semiconductor memory device, for example, process variations may affect the operational speed of the transistors comprising the individual memory cells. Additionally, process variations may affect the electrical characteristics, and hence the signal transfer time, of the bit line, which transfers the data signal from the memory cell to a clocked sense amplifier which determines what data was stored in the memory cell. This data signal transfer is controlled by a word line enable clock signal, which enables the output of the memory cell, and a sense clock signal, which enables the clocked sense amplifier to sense the data transferred via the bit lines.
In known memory devices, an additional amount of time is added to the calculated amount of delay between an active word line enable clock signal and an active sense clock signal that should permit normal, error-free operation. Such a calculated amount of delay corresponds to the amount of time required for the data signal to be transferred from the memory cell to the clocked sense amplifier, via the bit lines, in a device manufactured under the exact process conditions specified by the designer. The additional amount of time (i.e., time added as a design margin) is added to increase device yield by allowing for slower data signal transfers due to process variations, which may be well within specified tolerances. The drawback of increasing process yield by adding such a design margin time is that all devices are slower, even though some devices may operate internally at a higher speed.
Therefore, it is an object of the present invention to provide a method and circuit for automatically compensating a delay circuit, which is used to delay an input clock signal, in proportion to signal transfer speed variations due to process variations in the manufacture of semiconductor devices.
It is another object of the present invention to provide such a method and circuit for compensating a delay circuit used in generating a sense amplifier clock, relative to enabling of a word line, in random access memories such as static random access memories (SRAM) and dynamic random-access memories (DRAMs), and read-only memories (ROMs) of various types, including programmable ROMs such as EPROMs, EEPROMs, EAROMs, and the like.
It is another object of the present invention to provide such a method and circuit for compensating the sense amplifier clock delay circuit to account for the threshold drop across the access transistors in such an SRAM, such threshold drop slowing the bit line separation in a memory read operation.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.